1. Field of the Invention
The present invention relates to integrated circuit technology.
2. The Prior Art
Snap back has been a problem in integrated circuits when voltage exceeding the junction breakdown of transistor devices is present in an integrated circuit. This problem is presently dealt with by providing guard ring structures as is known in the art. Guard ring structures only minimize but do not eliminate the snap back.
In circuits such as non-volatile memory, high voltage P-channel and N-channel MOS transistor devices are used to form latch circuits to store write data. The high voltage N-channel device is leaky, resulting in standby current flowing during standby. This also causes the latch circuit to flip states during high voltage operation, resulting in data corruption.
The flipping stage and data corruption in the high-voltage latch circuits are caused by snap back of the high-voltage N-channel or P-Channel device during high voltage operation. When the drain of the high-voltage N-channel device is at the breakdown voltage of the N-channel device, breakdown occurs causing a large current to flow into the substrate. The parasitic NPN bipolar device at the bottom of the high-voltage N-channel device can be triggered on by the large substrate current. As the parasitic NPN transistor turns on, a low-impedance path exists at the logic “1” node to ground, pulling down the voltage and causing the latch circuit to flip from a “1” state to a “0” state at the node. A similar situation can occur in PMOS structures, in which a parasitic PNP transistor can pull a low-voltage node to a high state.